Are Synopsys Layoffs a Harbinger of the AI-Assisted Design Era?

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While Synopsys’ lay off of 10% of its workforce amid its merger with Ansys is making waves in trade media, it has also sparked a broad debate about whether design automation and AI are also factors behind job cuts of this scale. EDA heavyweights like Synopsys are investing heavily in AI-first workflows that autonomously explore chip architectures, optimize layouts and reduce power leakage without manual tuning.

But let us first take a closer look at Synopsys’ $35 billion cash-and-stock acquisition of engineering design firm Ansys, and how this integration’s aim to create a leaner operating model is leading to nearly 2,000 well-paid job cuts.

The big cut

The merger between chip design toolmaker Synopsys and Ansys, specializing in multi-physics simulation software for aerospace, automotive and semiconductors, was aimed to create a chip-to-system design powerhouse.

However, the $35 billion takeover of Ansys comes with unintended consequences that management will face as it streamlines operations and eliminates functional overlaps.

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Synopsys had approximately 20,000 employees at the end of fiscal year 2024, while Ansys had 6,500 at that time. (Source: Synopsys)

In a way, the layoffs of this scale were inevitable when a large EDA firm was acquired by an even larger EDA outfit. In other words, the merger of two complex software portfolios and their corresponding organizational structures necessitated a major overhaul.

Factors beyond Ansys acquisition

The official version is that these layoffs are a necessary step to drive business efficiencies and redirect investment toward higher-growth areas. However, it is important to note that this workforce reduction has been on the cards since Synopsys’ earnings call in September 2025.

So, while the integration with Ansys is clearly a major catalyst, are there other factors at play in Synopsys’ largest workforce reduction in two decades? Industry watchers frequently point to Synopsys’ missing revenue estimates in the third quarter of 2025.

The Sunnyvale, California-based EDA house attributed the shortfall to a slowdown in China and a major foundry client setback. While the U.S. government lifted export restrictions on EDA tools in July 2025 after imposing them in May 2025, the six-week sanction had a severe impact on Synopsys’ balance sheet.

The sanction disrupted new chip design starts and made IC designers in China more cautious about their long-term commitments. China, Synopsys’ second-largest market after the U.S., still represented 14.2% of its sales in this quarter.

Besides China woes, Synopsys noted a slowdown in its design IP segment and difficulties faced by a major foundry client. According to a Reuters story, Synopsys invested significant resources to develop specialized IP for a foundry and was expecting returns in the second half of 2025.

However, this foundry client withdrew for several reasons, resulting in an 8% decline in IP business revenue at Synopsys. Though Synopsys has not named the foundry client, industry sources believe it is Intel, which has indicated plans to use the 18A process node primarily for internal purposes.

Are AI-driven EDA tools a factor?

Large acquisitions inevitably lead to job cuts, but with a workforce reduction of this scale, industry observers have started to contemplate whether the AI-based EDA platforms are also a factor. Especially when Synopsys posted an increase in design automation revenue of 23% in the third quarter, in which it missed revenue forecasts.

EDA toolmakers like Synopsys are shifting their focus toward greater automation, requiring fewer human engineers. These AI-driven EDA platforms redefine design efficiency and productivity by leveraging reinforcement learning and genAI capabilities to automate tasks like RTL generation and testbench creation.

Case in point: Synopsys.ai Copilot employs genAI capabilities in areas like formal assertion generation and RTL code generation to accelerate design and verification cycle times from days to hours. Moreover, design engineers can perform documentation searches and script generation in minutes instead of hours.

Synopsys.ai is an EDA suite that incorporates assistive genAI capabilities to accelerate design and verification cycles. (Source: Synopsys)

So, Synopsys, while boasting AI-driven productivity, could become an early manifestation of the much-talked-about premise that AI tools will replace human engineers. At the same time, however, it is not a full-fledged “AI takes human jobs” doomsday scenario. Apparently, design engineers are increasingly collaborating with AI platforms; they set the high-level design intent while AI handles the repetitive grunt work.

The dawn of a hybrid design era

EDA, once a near-monopoly with sticky revenues, is in the midst of a disruption driven by AI-assisted design toolsets. The mass layoffs at Synopsys could be a harbinger of a new era of semiconductor design driven by automation and AI-assisted toolsets.

That calls for design engineers to seek reinvention—a.k.a. skills reboot—at a time when traditional hierarchies of semiconductor design and verification are steadily disrupted. They must prepare for a hybrid setup in which they work in an AI-assisted environment to co-develop semiconductor products more efficiently and quickly.

More importantly, once the trickle-down effect of these AI-driven EDA toolsets reaches the doorstep of chip vendors, there could be a disruption on a much larger scale. So, design engineers must acquaint themselves with this new era of AI-driven semiconductor design sooner rather than later.

See also:

U.S. Restricts EDA Software Sales to China